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| Ceramic Package Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 S E H S D D3 j x 45o J68.B 68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 MIN 0.092 0.067 0.033 0.033 MAX 0.118 0.083 0.039 0.039 MILLIMETERS MIN 2.34 1.71 0.85 0.85 MAX 3.00 2.11 0.99 0.99 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/31/94 NOTES: B E3 E B2 B3 D D1 D2 0.072 Ref 0.006 0.940 0.022 0.960 1.83 Ref 0.15 23.88 0.56 24.38 0.800 BSC 0.400 BSC 0.695 0.940 0.705 0.960 20.32 BSC 10.16 BSC 17.65 23.88 17.91 24.38 h h A HEAT SINK BASE 0.010 S E F S A1 PLANE 1 PLANE 2 -ERECESSED LID 0.007 M E F S H S B1 D3 E E1 E2 E3 e e1 h j L 0.800 BSC 0.400 BSC 0.695 0.705 20.32 BSC 10.16 BSC 17.65 17.91 0.050 BSC 0.015 0.050 Ref 0.020 Ref 0.042 0.042 0.080 0.003 17 17 68 0.058 0.058 0.090 0.015 - 1.27 BSC 0.38 1.27 Ref 0.51 Ref 1.07 1.07 2.03 0.08 17 17 68 1.47 1.47 2.29 0.38 e L -HL3 L1 L2 L3 ND NE -FE1 B3 N E2 L2 B2 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across all of the ceramic layers to make electrical connection with the required plane 2 terminals. L1 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and required plane 2 terminals shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. e1 D1 D2 40 |
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